[all-commits] [llvm/llvm-project] a500f7: [SelectionDAG] Add FP_TO_UINT_SAT/FP_TO_SINT_SAT t...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a500f7f48fdb64def09cb3b7487759b0972f2347
      https://github.com/llvm/llvm-project/commit/a500f7f48fdb64def09cb3b7487759b0972f2347
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-01-09 (Sun, 09 Jan 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    M llvm/test/CodeGen/AArch64/fcvt_combine.ll
    M llvm/test/CodeGen/AArch64/fptoui-sat-scalar.ll
    M llvm/test/CodeGen/RISCV/double-convert.ll
    M llvm/test/CodeGen/RISCV/float-convert.ll
    M llvm/test/CodeGen/RISCV/half-convert.ll
    M llvm/test/CodeGen/Thumb2/mve-fptoui-sat-vector.ll
    M llvm/test/CodeGen/Thumb2/mve-vcvt-float-to-fixed.ll

  Log Message:
  -----------
  [SelectionDAG] Add FP_TO_UINT_SAT/FP_TO_SINT_SAT to computeKnownBits/computeNumSignBits.

These nodes should saturate to their saturating VT. We can use this
information to know the bits past the VT are all zeros or all sign bits.

I think we might only have test coverage for the unsigned case. I'll
verify and add tests.

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D116870