[all-commits] [llvm/llvm-project] 5297cb: [AMDGPU] Enable copy between VGPR and AGPR classes...

[Christudasan Devadasan via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5297cbf04532f61fe18570982f4f2a3095d08c13
      https://github.com/llvm/llvm-project/commit/5297cbf04532f61fe18570982f4f2a3095d08c13
  Author: Christudasan Devadasan <Christudasan.Devadasan at amd.com>
  Date:   2021-11-29 (Mon, 29 Nov 2021)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.h
    M llvm/test/CodeGen/AMDGPU/extend-phi-subrange-not-in-parent.mir
    A llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
    M llvm/test/CodeGen/AMDGPU/spill-agpr.ll
    A llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
    M llvm/test/CodeGen/AMDGPU/spill-vgpr-to-agpr.ll
    A llvm/test/CodeGen/AMDGPU/vector-spill-restore-to-other-vector-type.mir

  Log Message:
  -----------
  [AMDGPU] Enable copy between VGPR and AGPR classes during regalloc

Greedy register allocator prefers to move a constrained
live range into a larger allocatable class over spilling
them. This patch defines the necessary superclasses for
vector registers. For subtargets that support copy between
VGPRs and AGPRs, the vector register spills during regalloc
now become just copies.

Reviewed By: rampitec, arsenm

Differential Revision: https://reviews.llvm.org/D109301