[all-commits] [llvm/llvm-project] f1d834: [TwoAddressInstructionPass] Create register mappin...

[weiguozhi via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f1d8345a2ab3c343929212d1c62174cfaa46e71a
      https://github.com/llvm/llvm-project/commit/f1d8345a2ab3c343929212d1c62174cfaa46e71a
  Author: Guozhi Wei <carrot at google.com>
  Date:   2021-11-29 (Mon, 29 Nov 2021)

  Changed paths:
    M llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
    M llvm/test/CodeGen/ARM/fpclamptosat.ll
    M llvm/test/CodeGen/ARM/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
    M llvm/test/CodeGen/ARM/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
    M llvm/test/CodeGen/ARM/ssat.ll
    M llvm/test/CodeGen/ARM/usat.ll
    M llvm/test/CodeGen/SystemZ/int-div-01.ll
    M llvm/test/CodeGen/SystemZ/int-div-03.ll
    M llvm/test/CodeGen/SystemZ/int-div-04.ll
    M llvm/test/CodeGen/SystemZ/int-mul-08.ll
    M llvm/test/CodeGen/Thumb/srem-seteq-illegal-types.ll
    M llvm/test/CodeGen/X86/64-bit-shift-by-32-minus-y.ll
    M llvm/test/CodeGen/X86/8bit_cmov_of_trunc_promotion.ll
    M llvm/test/CodeGen/X86/atomic-unordered.ll
    M llvm/test/CodeGen/X86/avx512-shuffles/partial_permute.ll
    M llvm/test/CodeGen/X86/bitreverse.ll
    M llvm/test/CodeGen/X86/bmi2.ll
    M llvm/test/CodeGen/X86/bypass-slow-division-32.ll
    M llvm/test/CodeGen/X86/combine-bitselect.ll
    M llvm/test/CodeGen/X86/combine-sdiv.ll
    M llvm/test/CodeGen/X86/ctpop-combine.ll
    M llvm/test/CodeGen/X86/divide-by-constant.ll
    M llvm/test/CodeGen/X86/fpclamptosat.ll
    M llvm/test/CodeGen/X86/haddsub-3.ll
    M llvm/test/CodeGen/X86/haddsub-shuf.ll
    M llvm/test/CodeGen/X86/haddsub.ll
    M llvm/test/CodeGen/X86/horizontal-reduce-fadd.ll
    M llvm/test/CodeGen/X86/horizontal-sum.ll
    M llvm/test/CodeGen/X86/lzcnt-cmp.ll
    M llvm/test/CodeGen/X86/nontemporal-loads.ll
    M llvm/test/CodeGen/X86/omit-urem-of-power-of-two-or-zero-when-comparing-with-zero.ll
    M llvm/test/CodeGen/X86/pmulh.ll
    M llvm/test/CodeGen/X86/popcnt.ll
    M llvm/test/CodeGen/X86/pull-binop-through-shift.ll
    M llvm/test/CodeGen/X86/rem.ll
    M llvm/test/CodeGen/X86/sat-add.ll
    M llvm/test/CodeGen/X86/sdiv_fix_sat.ll
    M llvm/test/CodeGen/X86/setcc-combine.ll
    M llvm/test/CodeGen/X86/shift-combine.ll
    M llvm/test/CodeGen/X86/shl-crash-on-legalize.ll
    M llvm/test/CodeGen/X86/slow-pmulld.ll
    M llvm/test/CodeGen/X86/smul_fix.ll
    M llvm/test/CodeGen/X86/smul_fix_sat.ll
    M llvm/test/CodeGen/X86/srem-seteq-vec-nonsplat.ll
    M llvm/test/CodeGen/X86/sse3-avx-addsub-2.ll
    M llvm/test/CodeGen/X86/uadd_sat.ll
    M llvm/test/CodeGen/X86/uadd_sat_vec.ll
    M llvm/test/CodeGen/X86/umul-with-overflow.ll
    M llvm/test/CodeGen/X86/umul_fix.ll
    M llvm/test/CodeGen/X86/umul_fix_sat.ll
    M llvm/test/CodeGen/X86/urem-seteq-vec-nonsplat.ll
    M llvm/test/CodeGen/X86/vec-strict-cmp-128.ll
    M llvm/test/CodeGen/X86/vec_ctbits.ll
    M llvm/test/CodeGen/X86/vec_umulo.ll
    M llvm/test/CodeGen/X86/vector-bitreverse.ll
    M llvm/test/CodeGen/X86/vector-ext-logic.ll
    M llvm/test/CodeGen/X86/vector-fshl-128.ll
    M llvm/test/CodeGen/X86/vector-fshr-128.ll
    M llvm/test/CodeGen/X86/vector-idiv-sdiv-128.ll
    M llvm/test/CodeGen/X86/vector-lzcnt-128.ll
    M llvm/test/CodeGen/X86/vector-lzcnt-sub128.ll
    M llvm/test/CodeGen/X86/vector-narrow-binop.ll
    M llvm/test/CodeGen/X86/vector-popcnt-128-ult-ugt.ll
    M llvm/test/CodeGen/X86/vector-popcnt-128.ll
    M llvm/test/CodeGen/X86/vector-reduce-fadd-fast.ll
    M llvm/test/CodeGen/X86/vector-reduce-fmul-fast.ll
    M llvm/test/CodeGen/X86/vector-shift-ashr-128.ll
    M llvm/test/CodeGen/X86/vector-shift-ashr-sub128.ll
    M llvm/test/CodeGen/X86/vector-shift-lshr-128.ll
    M llvm/test/CodeGen/X86/vector-shift-lshr-sub128.ll
    M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bw.ll
    M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll
    M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll
    M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512vbmi.ll
    M llvm/test/CodeGen/X86/vector-trunc-packus.ll
    M llvm/test/CodeGen/X86/vector-trunc-ssat.ll
    M llvm/test/CodeGen/X86/vector-trunc-usat.ll
    M llvm/test/CodeGen/X86/vector-tzcnt-128.ll
    M llvm/test/CodeGen/X86/vselect-packss.ll

  Log Message:
  -----------
  [TwoAddressInstructionPass] Create register mapping for registers with multiple uses in the current MBB

Currently we create register mappings for registers used only once in current
MBB. For registers with multiple uses, when all the uses are in the current MBB,
we can also create mappings for them similarly according to the last use.
For example

    %reg101 = ...
            = ... reg101
    %reg103 = ADD %reg101, %reg102

We can create mapping between %reg101 and %reg103.

Differential Revision: https://reviews.llvm.org/D113193