[all-commits] [llvm/llvm-project] ac4e01: [SVE][CodeGen] Fix predicate for add/sub + element...

[kmclaughlin-arm via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ac4e01ea0eb06134e37fc5404af4face8a262807
      https://github.com/llvm/llvm-project/commit/ac4e01ea0eb06134e37fc5404af4face8a262807
  Author: Kerry McLaughlin <kerry.mclaughlin at arm.com>
  Date:   2021-10-18 (Mon, 18 Oct 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

  Log Message:
  -----------
  [SVE][CodeGen] Fix predicate for add/sub + element count patterns

The patterns added in D111441 should use the HasSVEorStreamingSVE
predicate. This changes one incorrect use of HasSVE with the new
patterns.