[all-commits] [llvm/llvm-project] f5056c: [AArch64] Improve shuffle vector by using wider types

[Andrew Wei via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f5056c8c16bb732a83ec12776e01915af717917b
      https://github.com/llvm/llvm-project/commit/f5056c8c16bb732a83ec12776e01915af717917b
  Author: Andrew Wei <weiwei64 at huawei.com>
  Date:   2021-10-18 (Mon, 18 Oct 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/concat-vector.ll
    A llvm/test/CodeGen/AArch64/neon-widen-shuffle.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-concat.ll

  Log Message:
  -----------
  [AArch64] Improve shuffle vector by using wider types

Try to widen element type to get a new mask value for a better permutation
sequence, so that we can use NEON shuffle instructions, such as zip1/2,
UZP1/2, TRN1/2, REV, INS, etc.
For example:
  shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 6, i32 7, i32 2, i32 3>
is equivalent to:
  shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 3, i32 1>
Finally, we can get:
  mov     v0.d[0], v1.d[1]

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D111619