[all-commits] [llvm/llvm-project] ff1318: [RISCV] Unify the arch string parsing logic to to ...

[Kito Cheng via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ff13189c5d0d96d0f955e9b1e951cf0ddc9e1d92
      https://github.com/llvm/llvm-project/commit/ff13189c5d0d96d0f955e9b1e951cf0ddc9e1d92
  Author: Kito Cheng <kito.cheng at sifive.com>
  Date:   2021-10-17 (Sun, 17 Oct 2021)

  Changed paths:
    M clang/include/clang/Basic/DiagnosticCommonKinds.td
    M clang/lib/Basic/Targets/RISCV.cpp
    M clang/lib/Basic/Targets/RISCV.h
    M clang/lib/Driver/ToolChains/Arch/RISCV.cpp
    M clang/test/Driver/riscv-abi.c
    M clang/test/Driver/riscv-arch.c
    M clang/test/Driver/riscv-features.c
    A llvm/include/llvm/Support/RISCVISAInfo.h
    M llvm/lib/Support/CMakeLists.txt
    A llvm/lib/Support/RISCVISAInfo.cpp
    M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
    M llvm/test/MC/RISCV/attribute-arch.s
    M llvm/test/MC/RISCV/attribute-with-insts.s
    M llvm/test/MC/RISCV/invalid-attribute.s

  Log Message:
  -----------
  [RISCV] Unify the arch string parsing logic to to RISCVISAInfo.

How many place you need to modify when implementing a new extension for RISC-V?

At least 7 places as I know:

- Add new SubtargetFeature at RISCV.td
- -march parser in RISCV.cpp
- RISCVTargetInfo::initFeatureMap at RISCV.cpp for handling feature vector.
- RISCVTargetInfo::getTargetDefines at RISCV.cpp for pre-define marco.
- Arch string parser for ELF attribute in RISCVAsmParser.cpp
- ELF attribute emittion in RISCVAsmParser.cpp, and make sure it's in
  canonical order...
- ELF attribute emittion in RISCVTargetStreamer.cpp, and again, must in
  canonical order...

And now, this patch provide an unified infrastructure for handling (almost)
everything of RISC-V arch string.

After this patch, you only need to update 2 places for implement an extension
for RISC-V:
- Add new SubtargetFeature at RISCV.td, hmmm, it's hard to avoid.
- Add new entry to RISCVSupportedExtension at RISCVISAInfo.cpp or
  SupportedExperimentalExtensions at RISCVISAInfo.cpp .

Most codes are come from existing -march parser, but with few new feature/bug
fixes:
- Accept version for -march, e.g. -march=rv32i2p0.
- Reject version info with `p` but without minor version number like `rv32i2p`.

Differential Revision: https://reviews.llvm.org/D105168