[all-commits] [llvm/llvm-project] 6ec644: [TTI][X86] Add SSE2 sub-128bit vXi16/32 and v2i64 ...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6ec644e2157d63acccacd877cf08c68d5836c169
      https://github.com/llvm/llvm-project/commit/6ec644e2157d63acccacd877cf08c68d5836c169
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2021-10-16 (Sat, 16 Oct 2021)

  Changed paths:
    M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
    M llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-2.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-2.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-2.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-2-indices-0u.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-2.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-2.ll
    M llvm/test/Transforms/LoopVectorize/X86/interleaving.ll
    M llvm/test/Transforms/LoopVectorize/X86/pr47437.ll

  Log Message:
  -----------
  [TTI][X86] Add SSE2 sub-128bit vXi16/32 and v2i64 stride 2 interleaved load costs

These cases use the same codegen as AVX2 (pshuflw/pshufd) for the sub-128bit vector deinterleaving, and unpcklqdq for v2i64.

It's going to take a while to add full interleaved cost coverage, but since these are the same for SSE2 -> AVX2 it should be an easy win.

Fixes PR47437

Differential Revision: https://reviews.llvm.org/D111938