[all-commits] [llvm/llvm-project] aefaf1: [TableGen] Fix both sides of '&&' are same

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: aefaf167588b38768b15c57f0f0bfccfb87a399f
      https://github.com/llvm/llvm-project/commit/aefaf167588b38768b15c57f0f0bfccfb87a399f
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-10-12 (Tue, 12 Oct 2021)

  Changed paths:
    M llvm/utils/TableGen/CodeGenDAGPatterns.cpp
    M llvm/utils/TableGen/CodeGenDAGPatterns.h

  Log Message:
  -----------
  [TableGen] Fix both sides of '&&' are same

The operand of the second any_of in EnforceSmallerThan should be
B not S like the FP code in the if below.

Unfortunately, fixing that causes an infinite loop in the build
of RISCV. So I've added a workaround for that as well.

Fixes PR44768.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D111502