[all-commits] [llvm/llvm-project] 67b105: [mlir][Vector] Allow a 0-d for for vector transfer...

[Nicolas Vasilache via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 67b10532c637b22c0926517d27f84759893a7258
      https://github.com/llvm/llvm-project/commit/67b10532c637b22c0926517d27f84759893a7258
  Author: Nicolas Vasilache <nicolas.vasilache at gmail.com>
  Date:   2021-10-12 (Tue, 12 Oct 2021)

  Changed paths:
    M mlir/include/mlir/Dialect/Vector/VectorOps.td
    M mlir/include/mlir/Interfaces/VectorInterfaces.td
    M mlir/lib/Dialect/Vector/VectorOps.cpp
    M mlir/lib/Dialect/Vector/VectorUtils.cpp
    M mlir/test/Dialect/Vector/invalid.mlir
    M mlir/test/Dialect/Vector/ops.mlir

  Log Message:
  -----------
  [mlir][Vector] Allow a 0-d for for vector transfer ops.

This revision updates the op semantics, printer, parser and verifier to allow 0-d transfers.
Until 0-d vectors are available, such transfers have a special form that transits through vector<1xt>.
This is a stepping stone towards the longer term work of adding 0-d vectors and will help significantly reduce corner cases in vectorization.

Transformations and lowerings do not yet support this form, extensions will follow.

Differential Revision: https://reviews.llvm.org/D111559