[all-commits] [llvm/llvm-project] 659996: [TwoAddressInstructionPass] Improve the SrcRegMap ...
weiguozhi via All-commits
all-commits at lists.llvm.org
Mon Oct 11 15:32:13 PDT 2021
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: 6599961c17073204ac868958e632cf4d92353cbe
https://github.com/llvm/llvm-project/commit/6599961c17073204ac868958e632cf4d92353cbe
Author: Guozhi Wei <carrot at google.com>
Date: 2021-10-11 (Mon, 11 Oct 2021)
Changed paths:
M llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
M llvm/test/CodeGen/ARM/ssat.ll
M llvm/test/CodeGen/ARM/usat.ll
M llvm/test/CodeGen/AVR/ctpop.ll
M llvm/test/CodeGen/AVR/hardware-mul.ll
M llvm/test/CodeGen/SystemZ/int-cmp-57.ll
M llvm/test/CodeGen/Thumb/pr35836_2.ll
M llvm/test/CodeGen/X86/DynamicCalleeSavedRegisters.ll
M llvm/test/CodeGen/X86/abs.ll
M llvm/test/CodeGen/X86/add-cmov.ll
M llvm/test/CodeGen/X86/addsub-constant-folding.ll
M llvm/test/CodeGen/X86/align-down.ll
M llvm/test/CodeGen/X86/arithmetic_fence2.ll
M llvm/test/CodeGen/X86/avg.ll
M llvm/test/CodeGen/X86/avx512-inc-dec.ll
M llvm/test/CodeGen/X86/avx512-mask-op.ll
M llvm/test/CodeGen/X86/avx512-regcall-NoMask.ll
M llvm/test/CodeGen/X86/avx512bw-mask-op.ll
M llvm/test/CodeGen/X86/avx512dq-mask-op.ll
M llvm/test/CodeGen/X86/bitreverse.ll
M llvm/test/CodeGen/X86/bswap_tree2.ll
M llvm/test/CodeGen/X86/cmp-concat.ll
M llvm/test/CodeGen/X86/combine-mul.ll
M llvm/test/CodeGen/X86/combine-mulo.ll
M llvm/test/CodeGen/X86/combine-or.ll
M llvm/test/CodeGen/X86/combine-sdiv.ll
M llvm/test/CodeGen/X86/combine-smax.ll
M llvm/test/CodeGen/X86/combine-smin.ll
M llvm/test/CodeGen/X86/combine-sra.ll
M llvm/test/CodeGen/X86/combine-srem.ll
M llvm/test/CodeGen/X86/combine-srl.ll
M llvm/test/CodeGen/X86/combine-udiv.ll
M llvm/test/CodeGen/X86/ctpop-combine.ll
M llvm/test/CodeGen/X86/fshl.ll
M llvm/test/CodeGen/X86/fshr.ll
M llvm/test/CodeGen/X86/funnel-shift.ll
M llvm/test/CodeGen/X86/haddsub-shuf.ll
M llvm/test/CodeGen/X86/haddsub-undef.ll
M llvm/test/CodeGen/X86/haddsub.ll
M llvm/test/CodeGen/X86/horizontal-reduce-fadd.ll
M llvm/test/CodeGen/X86/horizontal-sum.ll
M llvm/test/CodeGen/X86/i128-mul.ll
M llvm/test/CodeGen/X86/iabs.ll
M llvm/test/CodeGen/X86/imul.ll
M llvm/test/CodeGen/X86/midpoint-int-vec-128.ll
M llvm/test/CodeGen/X86/mul-constant-i16.ll
M llvm/test/CodeGen/X86/mul-constant-i32.ll
M llvm/test/CodeGen/X86/mul-constant-i64.ll
M llvm/test/CodeGen/X86/mul-constant-i8.ll
M llvm/test/CodeGen/X86/mul128.ll
M llvm/test/CodeGen/X86/overflow.ll
M llvm/test/CodeGen/X86/palignr.ll
M llvm/test/CodeGen/X86/phaddsub.ll
M llvm/test/CodeGen/X86/pmul.ll
M llvm/test/CodeGen/X86/pmulh.ll
M llvm/test/CodeGen/X86/popcnt.ll
M llvm/test/CodeGen/X86/powi.ll
M llvm/test/CodeGen/X86/pr42998.ll
M llvm/test/CodeGen/X86/recip-fastmath.ll
M llvm/test/CodeGen/X86/rev16.ll
M llvm/test/CodeGen/X86/rot16.ll
M llvm/test/CodeGen/X86/rotate-extract.ll
M llvm/test/CodeGen/X86/rotate-multi.ll
M llvm/test/CodeGen/X86/sat-add.ll
M llvm/test/CodeGen/X86/sdiv_fix.ll
M llvm/test/CodeGen/X86/select-constant-xor.ll
M llvm/test/CodeGen/X86/select.ll
M llvm/test/CodeGen/X86/shift-logic.ll
M llvm/test/CodeGen/X86/smax.ll
M llvm/test/CodeGen/X86/smin.ll
M llvm/test/CodeGen/X86/smul_fix_sat.ll
M llvm/test/CodeGen/X86/sqrt-fastmath-tune.ll
M llvm/test/CodeGen/X86/sqrt-fastmath.ll
M llvm/test/CodeGen/X86/sse-minmax.ll
M llvm/test/CodeGen/X86/sshl_sat.ll
M llvm/test/CodeGen/X86/ssub_sat.ll
M llvm/test/CodeGen/X86/ssub_sat_vec.ll
M llvm/test/CodeGen/X86/stack-folding-fp-avx512.ll
M llvm/test/CodeGen/X86/stack-folding-int-avx512.ll
M llvm/test/CodeGen/X86/tbm-intrinsics-fast-isel-x86_64.ll
M llvm/test/CodeGen/X86/tbm-intrinsics-fast-isel.ll
M llvm/test/CodeGen/X86/udiv_fix_sat.ll
M llvm/test/CodeGen/X86/umax.ll
M llvm/test/CodeGen/X86/umin.ll
M llvm/test/CodeGen/X86/umul_fix.ll
M llvm/test/CodeGen/X86/umul_fix_sat.ll
M llvm/test/CodeGen/X86/umulo-128-legalisation-lowering.ll
M llvm/test/CodeGen/X86/umulo-64-legalisation-lowering.ll
M llvm/test/CodeGen/X86/unfold-masked-merge-scalar-variablemask.ll
M llvm/test/CodeGen/X86/urem-lkk.ll
M llvm/test/CodeGen/X86/urem-seteq-vec-nonzero.ll
M llvm/test/CodeGen/X86/vec-strict-fptoint-128.ll
M llvm/test/CodeGen/X86/vec_ctbits.ll
M llvm/test/CodeGen/X86/vec_minmax_sint.ll
M llvm/test/CodeGen/X86/vec_minmax_uint.ll
M llvm/test/CodeGen/X86/vec_saddo.ll
M llvm/test/CodeGen/X86/vec_sdiv_to_shift.ll
M llvm/test/CodeGen/X86/vec_shift6.ll
M llvm/test/CodeGen/X86/vec_smulo.ll
M llvm/test/CodeGen/X86/vec_ssubo.ll
M llvm/test/CodeGen/X86/vec_umulo.ll
M llvm/test/CodeGen/X86/vector-bitreverse.ll
M llvm/test/CodeGen/X86/vector-ext-logic.ll
M llvm/test/CodeGen/X86/vector-fshl-128.ll
M llvm/test/CodeGen/X86/vector-fshl-rot-128.ll
M llvm/test/CodeGen/X86/vector-fshl-rot-sub128.ll
M llvm/test/CodeGen/X86/vector-fshr-128.ll
M llvm/test/CodeGen/X86/vector-fshr-rot-128.ll
M llvm/test/CodeGen/X86/vector-fshr-rot-sub128.ll
M llvm/test/CodeGen/X86/vector-idiv-udiv-128.ll
M llvm/test/CodeGen/X86/vector-lzcnt-128.ll
M llvm/test/CodeGen/X86/vector-mul.ll
M llvm/test/CodeGen/X86/vector-popcnt-128-ult-ugt.ll
M llvm/test/CodeGen/X86/vector-popcnt-128.ll
M llvm/test/CodeGen/X86/vector-reduce-fadd-fast.ll
M llvm/test/CodeGen/X86/vector-reduce-fadd.ll
M llvm/test/CodeGen/X86/vector-reduce-fmax.ll
M llvm/test/CodeGen/X86/vector-reduce-fmul-fast.ll
M llvm/test/CodeGen/X86/vector-reduce-fmul.ll
M llvm/test/CodeGen/X86/vector-reduce-smax.ll
M llvm/test/CodeGen/X86/vector-reduce-umax.ll
M llvm/test/CodeGen/X86/vector-rotate-128.ll
M llvm/test/CodeGen/X86/vector-shift-ashr-128.ll
M llvm/test/CodeGen/X86/vector-shift-ashr-sub128.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining.ll
M llvm/test/CodeGen/X86/vector-trunc-math.ll
M llvm/test/CodeGen/X86/vector-tzcnt-128.ll
M llvm/test/CodeGen/X86/vector-unsigned-cmp.ll
M llvm/test/CodeGen/X86/vselect-minmax.ll
M llvm/test/CodeGen/X86/vselect-zero.ll
M llvm/test/CodeGen/X86/x86-no_caller_saved_registers-preserve.ll
M llvm/test/CodeGen/X86/x86-shifts.ll
Log Message:
-----------
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
This patch contains following enhancements to SrcRegMap and DstRegMap:
1 In findOnlyInterestingUse not only check if the Reg is two address usage,
but also check after commutation can it be two address usage.
2 If a physical register is clobbered, remove SrcRegMap entries that are
mapped to it.
3 In processTiedPairs, when create a new COPY instruction, add a SrcRegMap
entry only when the COPY instruction is coalescable. (The COPY src is
killed)
With these enhancements isProfitableToCommute can do better commute decision,
and finally more register copies are removed.
Differential Revision: https://reviews.llvm.org/D108731
More information about the All-commits
mailing list