[all-commits] [llvm/llvm-project] c7e781: [RISCV] Add test cases showing failure to use ADDI...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c7e78150f733d5be3cae766de3385173e2e245ff
      https://github.com/llvm/llvm-project/commit/c7e78150f733d5be3cae766de3385173e2e245ff
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-09-22 (Wed, 22 Sep 2021)

  Changed paths:
    M llvm/test/CodeGen/RISCV/double-convert.ll
    M llvm/test/CodeGen/RISCV/float-convert.ll
    M llvm/test/CodeGen/RISCV/half-convert.ll

  Log Message:
  -----------
  [RISCV] Add test cases showing failure to use ADDIW before fcvt.s.w/fcvt.d.w/fcvt.h.w. NFC

By not using ADDIW we can cause both an ADDIW and ADDI to be emitted
when the add has multiple users.

These instructions needed be added to the list of instructions that
only use the lower 32 bits of input.

I've also added tests for the wu versions, but I'm having trouble
showing bad codegen from it.


  Commit: f0a422f935af877d8d9304eacbfbb6621e9ff643
      https://github.com/llvm/llvm-project/commit/f0a422f935af877d8d9304eacbfbb6621e9ff643
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-09-22 (Wed, 22 Sep 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/test/CodeGen/RISCV/double-convert.ll
    M llvm/test/CodeGen/RISCV/float-convert.ll
    M llvm/test/CodeGen/RISCV/half-convert.ll

  Log Message:
  -----------
  [RISCV] Add fcvt.s.w(u)/fcvt.d.w(u)/fcvt.h.w(u) to hasAllNBitUsers

These instructions only read the lower 32 bits of their input.


Compare: https://github.com/llvm/llvm-project/compare/cd36bab4ca90...f0a422f935af