[all-commits] [llvm/llvm-project] 34e055: [Clang][RISCV] Implement getConstraintRegister for...

[Luís Marques via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 34e055d33e37cd87b9f6f4b0431a4c061628d036
      https://github.com/llvm/llvm-project/commit/34e055d33e37cd87b9f6f4b0431a4c061628d036
  Author: Luís Marques <luismarques at lowrisc.org>
  Date:   2021-08-26 (Thu, 26 Aug 2021)

  Changed paths:
    M clang/lib/Basic/Targets/RISCV.h
    M clang/test/Sema/inline-asm-validate-riscv.c

  Log Message:
  -----------
  [Clang][RISCV] Implement getConstraintRegister for RISC-V

The getConstraintRegister method is used by semantic checking of inline
assembly statements in order to diagnose conflicts between clobber list
and input/output lists. By overriding getConstraintRegister we get those
diagnostics and we match RISC-V GCC's behavior. The implementation is
trivial due to the lack of single-register RISC-V-specific constraints.

Differential Revision: https://reviews.llvm.org/D108624