[all-commits] [llvm/llvm-project] 827dd1: [AMDGPU] Invert partial vgpr to agpr spill lane order

[Stanislav Mekhanoshin via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 827dd17e262472a98982565406431454231b556d
      https://github.com/llvm/llvm-project/commit/827dd17e262472a98982565406431454231b556d
  Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
  Date:   2021-08-26 (Thu, 26 Aug 2021)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
    M llvm/test/CodeGen/AMDGPU/pei-build-spill-partial-agpr.mir
    M llvm/test/CodeGen/AMDGPU/pei-build-spill.mir
    M llvm/test/CodeGen/AMDGPU/spill-agpr.mir
    A llvm/test/CodeGen/AMDGPU/spill-to-agpr-partial.mir

  Log Message:
  -----------
  [AMDGPU] Invert partial vgpr to agpr spill lane order

On targets requiring VGPR alignment we may end up spilling an
unaligned register if we were partially spilled odd number of
leading lanes. The reminder will start with an odd register.

This problem is solved by inverting the order of lanes to
be spillied so that we start from the end.

Differential Revision: https://reviews.llvm.org/D108732