[all-commits] [llvm/llvm-project] 20e626: [RISCV] Improve constant materialization for store...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 20e62658735a1b03ecadc3072593753abca21fd0
      https://github.com/llvm/llvm-project/commit/20e62658735a1b03ecadc3072593753abca21fd0
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-08-18 (Wed, 18 Aug 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
    M llvm/test/CodeGen/RISCV/calling-conv-half.ll
    M llvm/test/CodeGen/RISCV/imm.ll

  Log Message:
  -----------
  [RISCV] Improve constant materialization for stores of i16 or i32 negative constants.

DAGCombiner::visitStore can clear the upper bits of constants
used by stores. This leads prevents them from being recognized as
sign extended negative values making them more expensive to
materialize.

This patch uses the hasAllNBitUsers method from D107658 to make
a negative constant if none of the users care about the upper bits.

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D108052