[all-commits] [llvm/llvm-project] d9ba1a: [RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d9ba1a9c5cac638a5cf3d23404509f7eeb434b7a
      https://github.com/llvm/llvm-project/commit/d9ba1a9c5cac638a5cf3d23404509f7eeb434b7a
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-08-18 (Wed, 18 Aug 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoM.td
    M llvm/test/CodeGen/RISCV/add-before-shl.ll
    M llvm/test/CodeGen/RISCV/add-imm.ll
    M llvm/test/CodeGen/RISCV/addimm-mulimm.ll
    M llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
    M llvm/test/CodeGen/RISCV/atomic-rmw.ll
    M llvm/test/CodeGen/RISCV/atomic-signext.ll
    M llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
    M llvm/test/CodeGen/RISCV/div.ll
    M llvm/test/CodeGen/RISCV/mul.ll
    M llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll
    M llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll
    M llvm/test/CodeGen/RISCV/rv64i-w-insts-legalization.ll
    M llvm/test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll
    M llvm/test/CodeGen/RISCV/rv64zbb-zbp.ll
    M llvm/test/CodeGen/RISCV/rv64zbb.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
    M llvm/test/CodeGen/RISCV/sadd_sat_plus.ll
    M llvm/test/CodeGen/RISCV/shadowcallstack.ll
    M llvm/test/CodeGen/RISCV/shift-masked-shamt.ll
    M llvm/test/CodeGen/RISCV/srem-lkk.ll
    M llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
    M llvm/test/CodeGen/RISCV/srem-vector-lkk.ll
    M llvm/test/CodeGen/RISCV/ssub_sat_plus.ll
    M llvm/test/CodeGen/RISCV/uadd_sat_plus.ll
    M llvm/test/CodeGen/RISCV/urem-lkk.ll
    M llvm/test/CodeGen/RISCV/urem-vector-lkk.ll
    M llvm/test/CodeGen/RISCV/usub_sat_plus.ll
    M llvm/test/CodeGen/RISCV/vararg.ll
    M llvm/test/CodeGen/RISCV/xaluo.ll

  Log Message:
  -----------
  [RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used.

We normally select these when the root node is a sext_inreg, but
SimplifyDemandedBits can sometimes bypass the sext_inreg for some
users. This can create situation where sext_inreg+add/sub/mul/shl
is selected to a W instruction, and then the add/sub/mul/shl is
separately selected to a non-W instruction with the same inputs.

This patch tries to detect when it would still be ok to use a W
instruction without the sext_inreg by checking the direct users.
This can allow the W instruction to CSE with one created for a
sext_inreg+add/sub/mul/shl. To minimize complexity and cost of
checking, we make no attempt to determine if the CSE will happen
and just always use a W instruction when we can.

Differential Revision: https://reviews.llvm.org/D107658