[all-commits] [llvm/llvm-project] 52e0cf: [ARM] Enable subreg liveness

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 52e0cf9d61618353d2745a51a16ae408edf0f49b
      https://github.com/llvm/llvm-project/commit/52e0cf9d61618353d2745a51a16ae408edf0f49b
  Author: David Green <david.green at arm.com>
  Date:   2021-08-17 (Tue, 17 Aug 2021)

  Changed paths:
    M llvm/lib/Target/ARM/ARMSubtarget.cpp
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/lsr-profitable-chain.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-operand.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-intrinsic-round.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/unpredload.ll
    M llvm/test/CodeGen/Thumb2/active_lane_mask.ll
    M llvm/test/CodeGen/Thumb2/mve-be.ll
    M llvm/test/CodeGen/Thumb2/mve-ctlz.ll
    M llvm/test/CodeGen/Thumb2/mve-ctpop.ll
    M llvm/test/CodeGen/Thumb2/mve-cttz.ll
    M llvm/test/CodeGen/Thumb2/mve-div-expand.ll
    M llvm/test/CodeGen/Thumb2/mve-float16regloops.ll
    M llvm/test/CodeGen/Thumb2/mve-float32regloops.ll
    M llvm/test/CodeGen/Thumb2/mve-fmas.ll
    M llvm/test/CodeGen/Thumb2/mve-fmath.ll
    M llvm/test/CodeGen/Thumb2/mve-fp-negabs.ll
    M llvm/test/CodeGen/Thumb2/mve-frint.ll
    M llvm/test/CodeGen/Thumb2/mve-gather-ind16-scaled.ll
    M llvm/test/CodeGen/Thumb2/mve-gather-ptrs.ll
    M llvm/test/CodeGen/Thumb2/mve-intrinsics/vld24.ll
    M llvm/test/CodeGen/Thumb2/mve-laneinterleaving-cost.ll
    M llvm/test/CodeGen/Thumb2/mve-laneinterleaving.ll
    M llvm/test/CodeGen/Thumb2/mve-masked-ldst.ll
    M llvm/test/CodeGen/Thumb2/mve-masked-store.ll
    M llvm/test/CodeGen/Thumb2/mve-minmax.ll
    M llvm/test/CodeGen/Thumb2/mve-nofloat.ll
    M llvm/test/CodeGen/Thumb2/mve-phireg.ll
    M llvm/test/CodeGen/Thumb2/mve-postinc-dct.ll
    M llvm/test/CodeGen/Thumb2/mve-pred-build-var.ll
    M llvm/test/CodeGen/Thumb2/mve-pred-shuffle.ll
    M llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll
    M llvm/test/CodeGen/Thumb2/mve-scatter-ind16-scaled.ll
    M llvm/test/CodeGen/Thumb2/mve-scatter-ind16-unscaled.ll
    M llvm/test/CodeGen/Thumb2/mve-scatter-ind32-unscaled.ll
    M llvm/test/CodeGen/Thumb2/mve-scatter-ptrs.ll
    M llvm/test/CodeGen/Thumb2/mve-sext-masked-load.ll
    M llvm/test/CodeGen/Thumb2/mve-shuffle.ll
    M llvm/test/CodeGen/Thumb2/mve-shuffleext.ll
    M llvm/test/CodeGen/Thumb2/mve-shufflemov.ll
    M llvm/test/CodeGen/Thumb2/mve-simple-arith.ll
    M llvm/test/CodeGen/Thumb2/mve-soft-float-abi.ll
    M llvm/test/CodeGen/Thumb2/mve-vabdus.ll
    M llvm/test/CodeGen/Thumb2/mve-vcmpf.ll
    M llvm/test/CodeGen/Thumb2/mve-vcmpfr.ll
    M llvm/test/CodeGen/Thumb2/mve-vcmpfz.ll
    M llvm/test/CodeGen/Thumb2/mve-vcvt.ll
    M llvm/test/CodeGen/Thumb2/mve-vcvt16.ll
    M llvm/test/CodeGen/Thumb2/mve-vdup.ll
    M llvm/test/CodeGen/Thumb2/mve-vecreduce-fadd.ll
    M llvm/test/CodeGen/Thumb2/mve-vecreduce-fminmax.ll
    M llvm/test/CodeGen/Thumb2/mve-vecreduce-fmul.ll
    M llvm/test/CodeGen/Thumb2/mve-vecreduce-loops.ll
    M llvm/test/CodeGen/Thumb2/mve-vhadd.ll
    M llvm/test/CodeGen/Thumb2/mve-vld2-post.ll
    M llvm/test/CodeGen/Thumb2/mve-vld2.ll
    M llvm/test/CodeGen/Thumb2/mve-vld3.ll
    M llvm/test/CodeGen/Thumb2/mve-vld4-post.ll
    M llvm/test/CodeGen/Thumb2/mve-vld4.ll
    M llvm/test/CodeGen/Thumb2/mve-vldshuffle.ll
    M llvm/test/CodeGen/Thumb2/mve-vldst4.ll
    M llvm/test/CodeGen/Thumb2/mve-vmovn.ll
    M llvm/test/CodeGen/Thumb2/mve-vmovnstore.ll
    M llvm/test/CodeGen/Thumb2/mve-vmull-splat.ll
    M llvm/test/CodeGen/Thumb2/mve-vst2-post.ll
    M llvm/test/CodeGen/Thumb2/mve-vst2.ll
    M llvm/test/CodeGen/Thumb2/mve-vst3.ll
    M llvm/test/CodeGen/Thumb2/mve-vst4-post.ll
    M llvm/test/CodeGen/Thumb2/mve-vst4.ll
    M llvm/test/CodeGen/Thumb2/mve-zext-masked-load.ll

  Log Message:
  -----------
  [ARM] Enable subreg liveness

This enables subreg liveness in the arm backend when MVE is present,
which allows the register allocator to detect when subregister are
alive/dead, compared to only acting on full registers. This can helps
produce better code on MVE with the way MQPR registers are made up of
SPR registers, but is especially helpful for MQQPR and MQQQQPR
registers, where there are very few "registers" available and being able
to split them up into subregs can help produce much better code.

Differential Revision: https://reviews.llvm.org/D107642