[all-commits] [llvm/llvm-project] 62e892: [ARM] Add MQQPR and MQQQQPR spill and reload pseud...

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 62e892fa2d4f372fddc5e4ef5134830f8fa20062
      https://github.com/llvm/llvm-project/commit/62e892fa2d4f372fddc5e4ef5134830f8fa20062
  Author: David Green <david.green at arm.com>
  Date:   2021-08-17 (Tue, 17 Aug 2021)

  Changed paths:
    M llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
    M llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
    M llvm/lib/Target/ARM/ARMInstrMVE.td

  Log Message:
  -----------
  [ARM] Add MQQPR and MQQQQPR spill and reload pseudo instructions

As a part of D107642, this adds pseudo instructions for MQQPR and
MQQQQPR register classes, that can spill and reloads entire registers
whilst keeping them combined, not splitting them into multiple D subregs
that a VLDMIA/VSTMIA would use. This can help certain analyses, and
helps to prevent verifier issues with subreg liveness.