[all-commits] [llvm/llvm-project] 8b3383: [RISCV] Rename vector inline constraint from 'v' t...

[Kai Wang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8b33839f010fe780fdaf68160be7c45d07fdfcad
      https://github.com/llvm/llvm-project/commit/8b33839f010fe780fdaf68160be7c45d07fdfcad
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2021-08-01 (Sun, 01 Aug 2021)

  Changed paths:
    M clang/lib/Basic/Targets/RISCV.cpp
    M clang/test/CodeGen/RISCV/riscv-inline-asm-rvv.c
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/inline-asm.ll

  Log Message:
  -----------
  [RISCV] Rename vector inline constraint from 'v' to 'vr' and 'vm' in IR.

Differential Revision: https://reviews.llvm.org/D107139


  Commit: ee3aef93b73646ef98f0241498d807a4fb68b78c
      https://github.com/llvm/llvm-project/commit/ee3aef93b73646ef98f0241498d807a4fb68b78c
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2021-08-01 (Sun, 01 Aug 2021)

  Changed paths:
    M llvm/docs/LangRef.rst

  Log Message:
  -----------
  [RISCV][Docs] Add description about inline asm constraint for V.

Add inline asm constraint 'vr' for vector registers and 'vm' for vector
mask registers.

Differential Revision: https://reviews.llvm.org/D106633


Compare: https://github.com/llvm/llvm-project/compare/bdd55b2f1810...ee3aef93b736