[all-commits] [llvm/llvm-project] bdd55b: Fix the default alignment of i1 vectors.

[Eli Friedman via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: bdd55b2f1810eb5a2474a36229d08a9e5ca870fc
      https://github.com/llvm/llvm-project/commit/bdd55b2f1810eb5a2474a36229d08a9e5ca870fc
  Author: Eli Friedman <efriedma at quicinc.com>
  Date:   2021-07-31 (Sat, 31 Jul 2021)

  Changed paths:
    M clang/test/CodeGen/attr-arm-sve-vector-bits-bitcast.c
    M clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
    M clang/test/CodeGen/attr-arm-sve-vector-bits-cast.c
    M clang/test/CodeGen/attr-arm-sve-vector-bits-codegen.c
    M clang/test/CodeGen/attr-arm-sve-vector-bits-globals.c
    M clang/test/CodeGen/builtins-ppc-pair-mma.c
    M llvm/lib/IR/DataLayout.cpp
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/test/CodeGen/AArch64/GlobalISel/ret-vec-promote.ll
    M llvm/test/CodeGen/AArch64/spillfill-sve.ll
    M llvm/test/CodeGen/AArch64/sve-calling-convention-byref.ll
    M llvm/test/CodeGen/AMDGPU/lower-kernargs.ll
    M llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
    M llvm/test/CodeGen/NVPTX/param-load-store.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
    M llvm/test/CodeGen/Thumb2/mve-masked-ldst.ll
    M llvm/test/CodeGen/Thumb2/mve-masked-load.ll
    M llvm/test/CodeGen/Thumb2/mve-masked-store.ll
    M llvm/test/CodeGen/Thumb2/mve-pred-bitcast.ll
    M llvm/test/CodeGen/X86/avx512-extract-subvector-load-store.ll
    M llvm/test/CodeGen/X86/avx512-mask-op.ll
    M llvm/test/CodeGen/X86/avx512-select.ll
    M llvm/test/CodeGen/X86/bitcast-vector-bool.ll
    M llvm/test/CodeGen/X86/load-local-v3i129.ll
    M llvm/test/CodeGen/X86/pr41619.ll
    M llvm/test/CodeGen/X86/vector-sext.ll
    M llvm/test/Transforms/InstCombine/abs-intrinsic.ll
    M llvm/test/Transforms/InstCombine/icmp-vec.ll
    M llvm/test/Transforms/InstCombine/select-min-max.ll
    M llvm/test/Transforms/InstCombine/shufflevec-bitcast.ll
    M llvm/test/Transforms/SROA/vector-promotion-different-size.ll
    M llvm/test/Transforms/VectorCombine/load-insert-store.ll

  Log Message:
  -----------
  Fix the default alignment of i1 vectors.

Currently, the default alignment is much larger than the actual size of
the vector in memory.  Fix this to use a sane default.

For SVE, temporarily remove lowering of load/store operations for
predicates with less than 16 elements. The layout the backend was
assuming for SVE predicates with less than 16 elements doesn't agree
with the frontend. More work probably needs to be done here.

This change is, strictly speaking, not backwards-compatible at the
bitcode level. But probably nobody is actually depending on that; i1
vectors in memory are rare, and the code that does use them probably
ends up forcing the alignment to something sane anyway.  If we think
this is a concern, I can restrict this to scalable vectors for now
(where it's actually causing issues for me at the moment).

Differential Revision: https://reviews.llvm.org/D88994