[all-commits] [llvm/llvm-project] 00c1cc: [RISCV] Add more i32 srem/sdiv with power of 2 con...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 00c1cc867fbccf46166de0b9f6975f31c59ee540
      https://github.com/llvm/llvm-project/commit/00c1cc867fbccf46166de0b9f6975f31c59ee540
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-07-18 (Sun, 18 Jul 2021)

  Changed paths:
    M llvm/test/CodeGen/RISCV/div.ll
    M llvm/test/CodeGen/RISCV/rem.ll

  Log Message:
  -----------
  [RISCV] Add more i32 srem/sdiv with power of 2 constant tests. NFC

Add a small power 2 srem test to match existing sdiv test. Add
larger power of 2 test to both.

The larger constant test shows materialization of a constant
for an AND in the RV64 code. We should be using W shift instructions
to match the RV32 code.