[all-commits] [llvm/llvm-project] 173332: [RISCV] Manually emit the best shift for VSCALE lo...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 173332d175614561770469d237f8c5ba6378a0e7
      https://github.com/llvm/llvm-project/commit/173332d175614561770469d237f8c5ba6378a0e7
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-07-17 (Sat, 17 Jul 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll
    M llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
    M llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/rvv-vscale.i32.ll
    M llvm/test/CodeGen/RISCV/rvv/rvv-vscale.i64.ll
    M llvm/test/CodeGen/RISCV/rvv/stepvector.ll
    M llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv64.ll

  Log Message:
  -----------
  [RISCV] Manually emit the best shift for VSCALE lowering to improve codegen.

We assume VLENB is a multiple of 8 and previously relied on shift
pairs being optimized to an AND+SHL/SHR and computeKnownBits
removing the AND. This doesn't happen if (vlenb >> 3) gets CSEd
to have multiple uses. This patch manually emits the best shift
to workaround this.