[all-commits] [llvm/llvm-project] ba627a: [PowerPC] Update Refactored Load/Store Implementat...

Fri Jul 16 07:29:28 PDT 2021

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ba627a32e125cab988f97da8e2466398f2bc75b2
      https://github.com/llvm/llvm-project/commit/ba627a32e125cab988f97da8e2466398f2bc75b2
  Author: Amy Kwan <amy.kwan1 at ibm.com>
  Date:   2021-07-16 (Fri, 16 Jul 2021)

  Changed paths:
    M llvm/lib/Target/PowerPC/PPCInstrVSX.td
    M llvm/test/CodeGen/PowerPC/PR33671.ll
    M llvm/test/CodeGen/PowerPC/VSX-XForm-Scalars.ll
    M llvm/test/CodeGen/PowerPC/aix-dfltabi-rsrvd-reg.ll
    M llvm/test/CodeGen/PowerPC/aix-p9-insert-extract.ll
    M llvm/test/CodeGen/PowerPC/aix-vec-arg-spills-callee.ll
    M llvm/test/CodeGen/PowerPC/aix-vector-vararg-fixed-caller.ll
    M llvm/test/CodeGen/PowerPC/aix32-vector-vararg-fixed-callee.ll
    M llvm/test/CodeGen/PowerPC/aix64-vector-vararg-fixed-callee.ll
    M llvm/test/CodeGen/PowerPC/build-vector-tests.ll
    M llvm/test/CodeGen/PowerPC/builtins-ppc-p9-f128.ll
    M llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll
    M llvm/test/CodeGen/PowerPC/constant-pool.ll
    M llvm/test/CodeGen/PowerPC/ctrloop-constrained-fp.ll
    M llvm/test/CodeGen/PowerPC/extract-and-store.ll
    M llvm/test/CodeGen/PowerPC/f128-aggregates.ll
    M llvm/test/CodeGen/PowerPC/f128-arith.ll
    M llvm/test/CodeGen/PowerPC/f128-compare.ll
    M llvm/test/CodeGen/PowerPC/f128-conv.ll
    M llvm/test/CodeGen/PowerPC/f128-passByValue.ll
    M llvm/test/CodeGen/PowerPC/f128-truncateNconv.ll
    M llvm/test/CodeGen/PowerPC/f128_ldst.ll
    M llvm/test/CodeGen/PowerPC/fast-isel-load-store-vsx.ll
    M llvm/test/CodeGen/PowerPC/float-load-store-pair.ll
    M llvm/test/CodeGen/PowerPC/fma-combine.ll
    M llvm/test/CodeGen/PowerPC/fmf-propagation.ll
    M llvm/test/CodeGen/PowerPC/fp-strict-conv-f128.ll
    M llvm/test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll
    M llvm/test/CodeGen/PowerPC/instr-properties.ll
    M llvm/test/CodeGen/PowerPC/load-shuffle-and-shuffle-store.ll
    M llvm/test/CodeGen/PowerPC/lxv-aligned-stack-slots.ll
    M llvm/test/CodeGen/PowerPC/mcm-4.ll
    M llvm/test/CodeGen/PowerPC/mma-acc-spill.ll
    M llvm/test/CodeGen/PowerPC/mma-outer-product.ll
    M llvm/test/CodeGen/PowerPC/mul-const-vector.ll
    M llvm/test/CodeGen/PowerPC/non-debug-mi-search-frspxsrsp.ll
    M llvm/test/CodeGen/PowerPC/p10-splatImm-CPload-pcrel.ll
    M llvm/test/CodeGen/PowerPC/p10-vector-rotate.ll
    M llvm/test/CodeGen/PowerPC/p9-vinsert-vextract.ll
    M llvm/test/CodeGen/PowerPC/pcrel-linkeropt.ll
    M llvm/test/CodeGen/PowerPC/pcrel_ldst.ll
    M llvm/test/CodeGen/PowerPC/ppc64-align-long-double.ll
    M llvm/test/CodeGen/PowerPC/ppc64-i128-abi.ll
    M llvm/test/CodeGen/PowerPC/ppcf128-constrained-fp-intrinsics.ll
    M llvm/test/CodeGen/PowerPC/pr30715.ll
    M llvm/test/CodeGen/PowerPC/pr36292.ll
    M llvm/test/CodeGen/PowerPC/pr38087.ll
    M llvm/test/CodeGen/PowerPC/pr45628.ll
    M llvm/test/CodeGen/PowerPC/pre-inc-disable.ll
    M llvm/test/CodeGen/PowerPC/recipest.ll
    M llvm/test/CodeGen/PowerPC/register-pressure-reduction.ll
    M llvm/test/CodeGen/PowerPC/scalar-double-ldst.ll
    M llvm/test/CodeGen/PowerPC/scalar-float-ldst.ll
    M llvm/test/CodeGen/PowerPC/scalar-i16-ldst.ll
    M llvm/test/CodeGen/PowerPC/scalar-i32-ldst.ll
    M llvm/test/CodeGen/PowerPC/scalar-i64-ldst.ll
    M llvm/test/CodeGen/PowerPC/scalar-i8-ldst.ll
    M llvm/test/CodeGen/PowerPC/scalar_vector_test_1.ll
    M llvm/test/CodeGen/PowerPC/scalar_vector_test_2.ll
    M llvm/test/CodeGen/PowerPC/select_const.ll
    M llvm/test/CodeGen/PowerPC/srem-vector-lkk.ll
    M llvm/test/CodeGen/PowerPC/store_fptoi.ll
    M llvm/test/CodeGen/PowerPC/swaps-le-6.ll
    M llvm/test/CodeGen/PowerPC/tailcall-speculatable-callee.ll
    M llvm/test/CodeGen/PowerPC/toc-float.ll
    M llvm/test/CodeGen/PowerPC/unaligned-addressing-mode.ll
    M llvm/test/CodeGen/PowerPC/unaligned.ll
    M llvm/test/CodeGen/PowerPC/urem-vector-lkk.ll
    M llvm/test/CodeGen/PowerPC/vavg.ll
    M llvm/test/CodeGen/PowerPC/vec-itofp.ll
    M llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i16_elts.ll
    M llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i8_elts.ll
    M llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i16_elts.ll
    M llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i8_elts.ll
    M llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll
    M llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp64_elts.ll
    M llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll
    M llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp64_elts.ll
    M llvm/test/CodeGen/PowerPC/vec_extract_p9.ll
    M llvm/test/CodeGen/PowerPC/vec_int_ext.ll
    M llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll
    M llvm/test/CodeGen/PowerPC/vector-extend-sign.ll
    M llvm/test/CodeGen/PowerPC/vector-ldst.ll
    M llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll
    M llvm/test/CodeGen/PowerPC/vsx-p9.ll
    M llvm/test/CodeGen/PowerPC/vsx.ll
    M llvm/test/CodeGen/PowerPC/vsx_builtins.ll
    M llvm/test/CodeGen/PowerPC/vsx_insert_extract_le.ll
    M llvm/test/CodeGen/PowerPC/vsx_scalar_ld_st.ll

  Log Message:
  -----------
  [PowerPC] Update Refactored Load/Store Implementation, XForm VSX Patterns, and Tests

This patch includes the following updates to the load/store refactoring effort introduced in D93370:
 - Update various VSX patterns that use to "force" an XForm, to instead just XForm.
   This allows the ability for the patterns to compute the most optimal addressing
   mode (and to produce a DForm instruction when possible)
- Update pattern and test case for the LXVD2X/STXVD2X intrinsics
- Update LIT test cases that use to use the XForm instruction to use the DForm instruction

Differential Revision: https://reviews.llvm.org/D95115