[all-commits] [llvm/llvm-project] 99eb96: [AArch64][SME] Add load and store instructions

[Cullen Rhodes via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 99eb96f03186bf94476498979d5a6cd6a9cbf066
      https://github.com/llvm/llvm-project/commit/99eb96f03186bf94476498979d5a6cd6a9cbf066
  Author: Cullen Rhodes <cullen.rhodes at arm.com>
  Date:   2021-07-16 (Fri, 16 Jul 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrFormats.td
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
    M llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
    M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
    M llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
    M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
    M llvm/lib/Target/AArch64/SMEInstrFormats.td
    M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir
    M llvm/test/CodeGen/AArch64/stp-opt-with-renaming-reserved-regs.mir
    M llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir
    M llvm/test/MC/AArch64/SME/addha-diagnostics.s
    A llvm/test/MC/AArch64/SME/ld1b-diagnostics.s
    A llvm/test/MC/AArch64/SME/ld1b.s
    A llvm/test/MC/AArch64/SME/ld1d-diagnostics.s
    A llvm/test/MC/AArch64/SME/ld1d.s
    A llvm/test/MC/AArch64/SME/ld1h-diagnostics.s
    A llvm/test/MC/AArch64/SME/ld1h.s
    A llvm/test/MC/AArch64/SME/ld1q-diagnostics.s
    A llvm/test/MC/AArch64/SME/ld1q.s
    A llvm/test/MC/AArch64/SME/ld1w-diagnostics.s
    A llvm/test/MC/AArch64/SME/ld1w.s
    A llvm/test/MC/AArch64/SME/st1b-diagnostics.s
    A llvm/test/MC/AArch64/SME/st1b.s
    A llvm/test/MC/AArch64/SME/st1d-diagnostics.s
    A llvm/test/MC/AArch64/SME/st1d.s
    A llvm/test/MC/AArch64/SME/st1h-diagnostics.s
    A llvm/test/MC/AArch64/SME/st1h.s
    A llvm/test/MC/AArch64/SME/st1q-diagnostics.s
    A llvm/test/MC/AArch64/SME/st1q.s
    A llvm/test/MC/AArch64/SME/st1w-diagnostics.s
    A llvm/test/MC/AArch64/SME/st1w.s
    M llvm/test/MC/AArch64/neon-diagnostics.s

  Log Message:
  -----------
  [AArch64][SME] Add load and store instructions

This patch adds support for following contiguous load and store
instructions:

  * LD1B, LD1H, LD1W, LD1D, LD1Q
  * ST1B, ST1H, ST1W, ST1D, ST1Q

A new register class and operand is added for the 32-bit vector select
register W12-W15. The differences in the following tests which have been
re-generated are caused by the introduction of this register class:

  * llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll
  * llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir
  * llvm/test/CodeGen/AArch64/stp-opt-with-renaming-reserved-regs.mir
  * llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir

D88663 attempts to resolve the issue with the store pair test
differences in the AArch64 load/store optimizer.

The GlobalISel differences are caused by changes in the enum values of
register classes, tests have been updated with the new values.

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2021-06

Reviewed By: CarolineConcatto

Differential Revision: https://reviews.llvm.org/D105572