[all-commits] [llvm/llvm-project] f98ed7: [LSR] Handle case 1*reg => reg. PR50918

[Max Kazantsev via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f98ed74f6910f8b09e77497aeb30c860c433610d
      https://github.com/llvm/llvm-project/commit/f98ed74f6910f8b09e77497aeb30c860c433610d
  Author: Max Kazantsev <mkazantsev at azul.com>
  Date:   2021-07-16 (Fri, 16 Jul 2021)

  Changed paths:
    M llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
    A llvm/test/Transforms/LoopStrengthReduce/pr50918.ll

  Log Message:
  -----------
  [LSR] Handle case 1*reg => reg. PR50918

This patch addresses assertion failure in case when the only found formula for LSR
is `1*reg => reg` which was supposed to be an impossible situation, however there
is a test that shows it is possible.

In this case, we can use scale register with scale of 1 as the missing base register.

Reviewed By: huihuiz, reames
Differential Revision: https://reviews.llvm.org/D105009