[all-commits] [llvm/llvm-project] f5917e: [TableGen] Allow isAllocatable inheritence from an...

[Carl Ritson via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f5917e0312edacf1fe4cfebc532e3a78c854adee
      https://github.com/llvm/llvm-project/commit/f5917e0312edacf1fe4cfebc532e3a78c854adee
  Author: Carl Ritson <carl.ritson at amd.com>
  Date:   2021-07-16 (Fri, 16 Jul 2021)

  Changed paths:
    M llvm/utils/TableGen/CodeGenRegisters.cpp

  Log Message:
  -----------
  [TableGen] Allow isAllocatable inheritence from any superclass

When setting Allocatable on a generated register class check all
superclasses and set Allocatable true if any superclass is
allocatable.

Without this change generated register classes based on an
allocatable class may end up unallocatable due to the topological
inheritance order.

This change primarily effects AMDGPU backend; however, there are
a few changes in MIPs GlobalISel register constraints as a result.

Reviewed By: kparzysz

Differential Revision: https://reviews.llvm.org/D105967