[all-commits] [llvm/llvm-project] a8ad91: [X86] Fix handling of maskmovdqu in X32

[Harald van Dijk via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a8ad9170543906fc58336ab736a109fb42082fbf
      https://github.com/llvm/llvm-project/commit/a8ad9170543906fc58336ab736a109fb42082fbf
  Author: Harald van Dijk <harald at gigawatt.nl>
  Date:   2021-07-15 (Thu, 15 Jul 2021)

  Changed paths:
    M llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h
    M llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
    M llvm/lib/Target/X86/X86InstrSSE.td
    M llvm/lib/Target/X86/X86ScheduleBtVer2.td
    M llvm/test/CodeGen/X86/maskmovdqu.ll
    M llvm/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll
    A llvm/test/MC/X86/maskmovdqu.s
    A llvm/test/MC/X86/maskmovdqu64.s
    M llvm/utils/TableGen/X86DisassemblerTables.cpp
    M llvm/utils/TableGen/X86RecognizableInstr.cpp

  Log Message:
  -----------
  [X86] Fix handling of maskmovdqu in X32

The maskmovdqu instruction is an odd one: it has a 32-bit and a 64-bit
variant, the former using EDI, the latter RDI, but the use of the
register is implicit. In 64-bit mode, a 0x67 prefix can be used to get
the version using EDI, but there is no way to express this in
assembly in a single instruction, the only way is with an explicit
addr32.

This change adds support for the instruction. When generating assembly
text, that explicit addr32 will be added. When not generating assembly
text, it will be kept as a single instruction and will be emitted with
that 0x67 prefix. When parsing assembly text, it will be re-parsed as
ADDR32 followed by MASKMOVDQU64, which still results in the correct
bytes when converted to machine code.

The same applies to vmaskmovdqu as well.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D103427