[all-commits] [llvm/llvm-project] dad506: [ARM] Expand types handled in VQDMULH recognition

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: dad506bd4e27b52e671a8b927320845732e1e073
      https://github.com/llvm/llvm-project/commit/dad506bd4e27b52e671a8b927320845732e1e073
  Author: David Green <david.green at arm.com>
  Date:   2021-07-15 (Thu, 15 Jul 2021)

  Changed paths:
    M llvm/lib/Target/ARM/ARMISelLowering.cpp
    M llvm/test/CodeGen/Thumb2/mve-vqdmulh.ll

  Log Message:
  -----------
  [ARM] Expand types handled in VQDMULH recognition

We have a DAG combine for recognizing the sequence of nodes that make up
an MVE VQDMULH, but only currently handles specifically legal types.
This patch expands that to other power-2 vector types. For smaller than
legal types this means any_extending the type and casting it to a legal
type, using a VQDMULH where we only use some of the lanes. The result is
sign extended back to the original type, to properly set the invalid
lanes. Larger than legal types are split into chunks with extracts and
concat back together.

Differential Revision: https://reviews.llvm.org/D105814