[all-commits] [llvm/llvm-project] 25ee55: [SLP] match logical and/or as reduction candidates

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  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 25ee55c0baff316d3a7b1d7d2830a168af3fc46a
      https://github.com/llvm/llvm-project/commit/25ee55c0baff316d3a7b1d7d2830a168af3fc46a
  Author: Sanjay Patel <spatel at rotateright.com>
  Date:   2021-07-14 (Wed, 14 Jul 2021)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
    M llvm/test/Transforms/PhaseOrdering/X86/vector-reductions-logical.ll
    M llvm/test/Transforms/SLPVectorizer/X86/reduction-logical.ll

  Log Message:
  -----------
  [SLP] match logical and/or as reduction candidates

This has been a work-in-progress for a long time...we finally have all of
the pieces in place to handle vectorization of compare code as shown in:
https://llvm.org/PR41312

To do this (see PhaseOrdering tests), we converted SimplifyCFG and
InstCombine to the poison-safe (select) forms of the logic ops, so now we
need to have SLP recognize those patterns and insert a freeze op to make
a safe reduction:
https://alive2.llvm.org/ce/z/NH54Ah

We get the minimal patterns with this patch, but the PhaseOrdering tests
show that we still need adjustments to get the ideal IR in some or all of
the motivating cases.

Differential Revision: https://reviews.llvm.org/D105730