[all-commits] [llvm/llvm-project] 46e897: [RISCV] Prevent use of t0(aka x5) as rs1 for jalr ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 46e89708170c40e8cf0305b6de048ca879f43aab
      https://github.com/llvm/llvm-project/commit/46e89708170c40e8cf0305b6de048ca879f43aab
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-07-13 (Tue, 13 Jul 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
    M llvm/test/CodeGen/RISCV/calls.ll
    M llvm/test/CodeGen/RISCV/tail-calls.ll

  Log Message:
  -----------
  [RISCV] Prevent use of t0(aka x5) as rs1 for jalr instructions.

Some microarchitectures treat rs1=x1/x5 on jalr as a hint to pop
the return-address stack. We should avoid using x5 on jalr
instructions since we aren't using x5 as an alternate link register.

Differential Revision: https://reviews.llvm.org/D105875