[all-commits] [llvm/llvm-project] 6a3904: Mips: Mark special case calling convention handlin...

[Matt Arsenault via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6a3904f16e8e2095082f71e862a33266e10fa871
      https://github.com/llvm/llvm-project/commit/6a3904f16e8e2095082f71e862a33266e10fa871
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2021-07-13 (Tue, 13 Jul 2021)

  Changed paths:
    M llvm/lib/Target/Mips/MipsISelLowering.cpp
    M llvm/test/CodeGen/Mips/GlobalISel/irtranslator/float_args.ll
    M llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/float_args.ll

  Log Message:
  -----------
  Mips: Mark special case calling convention handling as custom

The number of registers used for passing f64 in some cases is context
dependent, and thus getNumRegistersForCallingConv is sometimes
inaccurate. For f64, it reports 1 but is sometimes split into 2 32-bit
registers.

For GlobalISel, the generic argument assignment code expects
getNumRegistersForCallingConv to return an accurate answer. Switch to
marking these arguments as custom so we can deal with this case as a
custom assignment rather.

This temporarily breaks a few globalisel tests which are fixed by a
future change to use more of the generic infrastructure.


  Commit: 121541fdcd5c9760ff242451d2b682c45a2a54df
      https://github.com/llvm/llvm-project/commit/121541fdcd5c9760ff242451d2b682c45a2a54df
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2021-07-13 (Tue, 13 Jul 2021)

  Changed paths:
    M llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h
    M llvm/lib/Target/ARM/ARMCallLowering.cpp
    M llvm/lib/Target/Mips/MipsCCState.cpp
    M llvm/lib/Target/Mips/MipsCCState.h
    M llvm/lib/Target/Mips/MipsCallLowering.cpp
    M llvm/lib/Target/Mips/MipsCallLowering.h
    M llvm/test/CodeGen/Mips/GlobalISel/irtranslator/extend_args.ll
    M llvm/test/CodeGen/Mips/GlobalISel/irtranslator/float_args.ll
    M llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/float_args.ll

  Log Message:
  -----------
  Mips/GlobalISel: Use more standard call lowering infrastructure

This also fixes some missing implicit uses on call instructions, adds
missing G_ASSERT_SEXT/ZEXT annotations, and some missing outgoing
sext/zexts. This also fixes not respecting tablegen requested type
promotions.

This starts treating f64 passed in i32 GPRs as a type of custom
assignment, which restores some previously XFAILed tests. This is due
to getNumRegistersForCallingConv returns a static value, but in this
case it is context dependent on other arguments.

Most of the ugliness is reproducing a hack CC_MipsO32 uses in
SelectionDAG. CC_MipsO32 depends on a bunch of vectors populated from
the original IR argument types in MipsCCState. The way this ends up
working in GlobalISel is it only ends up inspecting the most recently
added vector element. I'm pretty sure there are cleaner ways to do
this, but this seemed easier than fixing up the current DAG
handling. This is another case where it would be easier of the
CCAssignFns were passed the original type instead of only the
pre-legalized ones.

There's still a lot of junk here that shouldn't be necessary. This
also likely breaks big endian handling, but it wasn't complete/tested
anyway since the IRTranslator gives up on big endian targets.


  Commit: 77a608d9de472766fcab51412100764e534ceaf9
      https://github.com/llvm/llvm-project/commit/77a608d9de472766fcab51412100764e534ceaf9
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2021-07-13 (Tue, 13 Jul 2021)

  Changed paths:
    M llvm/include/llvm/CodeGen/GlobalISel/Utils.h
    M llvm/lib/CodeGen/GlobalISel/Utils.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp

  Log Message:
  -----------
  GlobalISel: Remove getIntrinsicID utility function

This is redundant with a method directly on MachineInstr


Compare: https://github.com/llvm/llvm-project/compare/0da95a5cf269...77a608d9de47