[all-commits] [llvm/llvm-project] 9e4267: [AArch64] Add target features for Armv9-A Scalable...

[Cullen Rhodes via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9e42675103e29642bf546c14b2272c9c2bb7c12c
      https://github.com/llvm/llvm-project/commit/9e42675103e29642bf546c14b2272c9c2bb7c12c
  Author: Cullen Rhodes <cullen.rhodes at arm.com>
  Date:   2021-07-12 (Mon, 12 Jul 2021)

  Changed paths:
    M llvm/include/llvm/Support/AArch64TargetParser.def
    M llvm/include/llvm/Support/AArch64TargetParser.h
    M llvm/lib/Support/AArch64TargetParser.cpp
    M llvm/lib/Target/AArch64/AArch64.td
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/lib/Target/AArch64/AArch64SchedA53.td
    M llvm/lib/Target/AArch64/AArch64SchedA57.td
    M llvm/lib/Target/AArch64/AArch64SchedCyclone.td
    M llvm/lib/Target/AArch64/AArch64SchedExynosM3.td
    M llvm/lib/Target/AArch64/AArch64SchedExynosM4.td
    M llvm/lib/Target/AArch64/AArch64SchedExynosM5.td
    M llvm/lib/Target/AArch64/AArch64SchedFalkor.td
    M llvm/lib/Target/AArch64/AArch64SchedKryo.td
    M llvm/lib/Target/AArch64/AArch64SchedThunderX.td
    M llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td
    M llvm/lib/Target/AArch64/AArch64Subtarget.h
    A llvm/test/MC/AArch64/SME/feature.s
    M llvm/unittests/Support/TargetParserTest.cpp

  Log Message:
  -----------
  [AArch64] Add target features for Armv9-A Scalable Matrix Extension (SME)

First patch in a series adding MC layer support for the Arm Scalable
Matrix Extension.

This patch adds the following features:

    sme, sme-i64, sme-f64

The sme-i64 and sme-f64 flags are for the optional I16I64 and F64F64
features.

If a target supports I16I64 then the following instructions are
implemented:

  * 64-bit integer ADDHA and ADDVA variants (D105570).
  * SMOPA, SMOPS, SUMOPA, SUMOPS, UMOPA, UMOPS, USMOPA, and USMOPS
    instructions that accumulate 16-bit integer outer products into 64-bit
    integer tiles.

If a target supports F64F64 then the FMOPA and FMOPS instructions that
accumulate double-precision floating-point outer products into
double-precision tiles are implemented.

Outer products are implemented in D105571.

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2021-06

Reviewed By: CarolineConcatto

Differential Revision: https://reviews.llvm.org/D105569