[all-commits] [llvm/llvm-project] 4b9d69: [InstCombine][tests] add tests for signbit + logic...

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  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4b9d698243c4170e4ecf7f4336cd2824d2641e2a
      https://github.com/llvm/llvm-project/commit/4b9d698243c4170e4ecf7f4336cd2824d2641e2a
  Author: Sanjay Patel <spatel at rotateright.com>
  Date:   2021-07-12 (Mon, 12 Jul 2021)

  Changed paths:
    M llvm/test/Transforms/InstCombine/icmp.ll

  Log Message:
  -----------
  [InstCombine][tests] add tests for signbit + logic; NFC

PR50816


  Commit: a488c7879e688f40647f0deacd7e09ec3082e4a4
      https://github.com/llvm/llvm-project/commit/a488c7879e688f40647f0deacd7e09ec3082e4a4
  Author: Sanjay Patel <spatel at rotateright.com>
  Date:   2021-07-12 (Mon, 12 Jul 2021)

  Changed paths:
    M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
    M llvm/test/Transforms/InstCombine/icmp.ll

  Log Message:
  -----------
  [InstCombine] reduce signbit test of logic ops to cmp with zero

This is the pattern from the description of:
https://llvm.org/PR50816

There might be a way to generalize this to a smaller or more
generic pattern, but I have not found it yet.

https://alive2.llvm.org/ce/z/ShzJoF

define i1 @src(i8 %x) {
  %add = add i8 %x, -1
  %xor = xor i8 %x, -1
  %and = and i8 %add, %xor
  %r = icmp slt i8 %and, 0
  ret i1 %r
}

define i1 @tgt(i8 %x) {
  %r = icmp eq i8 %x, 0
  ret i1 %r
}


Compare: https://github.com/llvm/llvm-project/compare/b4e843ba3a9e...a488c7879e68