[all-commits] [llvm/llvm-project] f73334: [AArch64] Set the latency of Cortex-A55 stores to 1

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f73334c46d59ffdbf12353932d5985049335a6c7
      https://github.com/llvm/llvm-project/commit/f73334c46d59ffdbf12353932d5985049335a6c7
  Author: David Green <david.green at arm.com>
  Date:   2021-07-12 (Mon, 12 Jul 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64SchedA55.td
    M llvm/test/tools/llvm-mca/AArch64/Cortex/A55-all-stats.s
    M llvm/test/tools/llvm-mca/AArch64/Cortex/A55-all-views.s
    M llvm/test/tools/llvm-mca/AArch64/Cortex/A55-basic-instructions.s
    M llvm/test/tools/llvm-mca/AArch64/Cortex/A55-in-order-retire.s
    M llvm/test/tools/llvm-mca/AArch64/Cortex/A55-load-store-alias.s
    M llvm/test/tools/llvm-mca/AArch64/Cortex/A55-out-of-order-retire.s

  Log Message:
  -----------
  [AArch64] Set the latency of Cortex-A55 stores to 1

This sets the latency of stores to 1 in the Cortex-A55 scheduling model,
to better match the values given in the software optimization guide.

The latency of a store in normal llvm scheduling does not appear to have
a lot of uses. If the store has no outputs then the latency is somewhat
meaningless (and pre/post increment update operands use the WriteAdr
write for those operands instead). The one place it does alter things is
the latency between a store and the end of the scheduling region, which
can in turn have an effect on the critical path length. As a result a
latency of 1 is more correct and offers ever-so-slightly better
scheduling of instructions near the end of the block.

They are marked as RetireOOO to keep the llvm-mca from introducing
stalls where non would exist.

Differential Revision: https://reviews.llvm.org/D105541