[all-commits] [llvm/llvm-project] c65371: [RISCV] Teach vsetvli insertion pass that operatio...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c653711fd3a9ac8399a435f02054ef42cddc4db7
      https://github.com/llvm/llvm-project/commit/c653711fd3a9ac8399a435f02054ef42cddc4db7
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-06-04 (Fri, 04 Jun 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
    M llvm/test/CodeGen/RISCV/rvv/saddo-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsge-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv64.ll

  Log Message:
  -----------
  [RISCV] Teach vsetvli insertion pass that operations on masks don't care about SEW/LMUL.

All that really matters is that the VLMAX of the preceding
instructions is the same as the VLMAX required by the mask
operation.

Also update the vmsge(u) handling to use the SEW/LMUL we use for
other mask register operations. We were matching it to the compare
before. Some cases will be improve if we fix masked compares to
use tail agnostic policy. I think they ignore the tail policy
anyway.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D103299