[all-commits] [llvm/llvm-project] 0718ac: [SDAG] allow cast folding for vector sext-of-setcc...

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  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0718ac706d4df719a0f019d1c0c3050c96ac2b8b
      https://github.com/llvm/llvm-project/commit/0718ac706d4df719a0f019d1c0c3050c96ac2b8b
  Author: Sanjay Patel <spatel at rotateright.com>
  Date:   2021-06-02 (Wed, 02 Jun 2021)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/X86/sext-vsetcc.ll

  Log Message:
  -----------
  [SDAG] allow cast folding for vector sext-of-setcc with signed compare

This extends 434c8e013a2c and ede3982792df to handle signed
predicates by sign-extending the setcc operands.

This is not shown directly in https://llvm.org/PR50055 ,
but the pattern is visible by changing the unsigned convert
to signed in the source code.