[all-commits] [llvm/llvm-project] 41ff1e: [RISCV] Improve register allocation for masked vwa...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 41ff1e0e29bbd3c12c8fdb0a0bbed8bda95dec85
      https://github.com/llvm/llvm-project/commit/41ff1e0e29bbd3c12c8fdb0a0bbed8bda95dec85
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-06-01 (Tue, 01 Jun 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv64.ll

  Log Message:
  -----------
  [RISCV] Improve register allocation for masked vwadd(u).wv, vwsub(u).wv, vfwadd.wv, and vfwsub.wv.

The first source has the same EEW as the destination, but we're
using earlyclobber which prevents them from ever being the same
register.

To workaround this, add a special TIED pseudo to use whenever the
first source and merge operand are the same value. This allows
us to use a single operand for the merge operand and first source
which we can then tie to the destination. A tied source disables
earlyclobber for that operand.

Reviewed By: arcbbb

Differential Revision: https://reviews.llvm.org/D103211