[all-commits] [llvm/llvm-project] 1b748f: [X86FixupLEAs] Transform the sequence LEA/SUB to S...
weiguozhi via All-commits
all-commits at lists.llvm.org
Tue Jun 1 10:33:14 PDT 2021
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: 1b748faf2bae246e2fc77d88420df13c2e60f4df
https://github.com/llvm/llvm-project/commit/1b748faf2bae246e2fc77d88420df13c2e60f4df
Author: Guozhi Wei <carrot at google.com>
Date: 2021-06-01 (Tue, 01 Jun 2021)
Changed paths:
M llvm/include/llvm/CodeGen/TargetInstrInfo.h
M llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
M llvm/lib/Target/X86/X86FixupLEAs.cpp
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Target/X86/X86InstrInfo.h
M llvm/test/CodeGen/X86/2009-03-23-MultiUseSched.ll
M llvm/test/CodeGen/X86/lea-opt2.ll
M llvm/test/CodeGen/X86/vp2intersect_multiple_pairs.ll
Log Message:
-----------
[X86FixupLEAs] Transform the sequence LEA/SUB to SUB/SUB
This patch transforms the sequence
lea (reg1, reg2), reg3
sub reg3, reg4
to two sub instructions
sub reg1, reg4
sub reg2, reg4
Similar optimization can also be applied to LEA/ADD sequence.
The modifications to TwoAddressInstructionPass is to ensure the operands of ADD
instruction has expected order (the dest register of LEA should be src register of ADD).
Differential Revision: https://reviews.llvm.org/D101970
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