[all-commits] [llvm/llvm-project] 896f9b: [RISCV] Remove earlyclobber from vnsrl/vnsra/vncli...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 896f9bc350eba0baf17f1ceae7383d88f0ce2a85
      https://github.com/llvm/llvm-project/commit/896f9bc350eba0baf17f1ceae7383d88f0ce2a85
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-06-01 (Tue, 01 Jun 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/test/CodeGen/RISCV/rvv/extload-truncstore.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnsra-vnsrl.ll
    M llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vnclip-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vnclip-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vnclipu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vnclipu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vnsra-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vnsra-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vnsrl-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vnsrl-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode-rv64.ll

  Log Message:
  -----------
  [RISCV] Remove earlyclobber from vnsrl/vnsra/vnclip(u) when the source and dest are a single vector register.

This guarantees they meet this overlap exception:

"The destination EEW is smaller than the source EEW and the overlap
is in the lowest-numbered part of the source register group"

Being a single register guarantees the overlap is always in the
lowerst-number part of the group.

Reviewed By: frasercrmck, khchen

Differential Revision: https://reviews.llvm.org/D103351