[all-commits] [llvm/llvm-project] 6cc78b: [ARM] Fix inline memcpy trip count sequence

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6cc78b9245bcc0e7a52723e2c298d290284e779b
      https://github.com/llvm/llvm-project/commit/6cc78b9245bcc0e7a52723e2c298d290284e779b
  Author: David Green <david.green at arm.com>
  Date:   2021-05-24 (Mon, 24 May 2021)

  Changed paths:
    M llvm/lib/Target/ARM/ARMISelLowering.cpp
    M llvm/test/CodeGen/Thumb2/mve-memtp-loop.ll
    M llvm/test/CodeGen/Thumb2/mve-phireg.ll
    M llvm/test/CodeGen/Thumb2/mve-tp-loop.mir

  Log Message:
  -----------
  [ARM] Fix inline memcpy trip count sequence

The trip count for a memcpy/memset will be n/16 rounded up to the
nearest integer. So (n+15)>>4. The old code was including a BIC too, to
clear one of the bits, which does not seem correct. This remove the
extra BIC.

Note that ideally this would never actually be generated, as in the
creation of a tail predicated loop we will DCE that setup code, letting
the WLSTP perform the trip count calculation. So this doesn't usually
come up in testing (and apparently the ARMLowOverheadLoops pass does not
do any sort of validation on the tripcount). Only if the generation of
the WLTP fails will it use the incorrect BIC instructions.

Differential Revision: https://reviews.llvm.org/D102629