[all-commits] [llvm/llvm-project] 778562: [X86][AVX] Add v4i64 shift-by-32 tests

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 778562ada39f5353b735c4ac204eddedb072a94b
      https://github.com/llvm/llvm-project/commit/778562ada39f5353b735c4ac204eddedb072a94b
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2021-05-12 (Wed, 12 May 2021)

  Changed paths:
    M llvm/test/CodeGen/X86/vector-shift-ashr-256.ll
    M llvm/test/CodeGen/X86/vector-shift-lshr-256.ll
    M llvm/test/CodeGen/X86/vector-shift-shl-256.ll

  Log Message:
  -----------
  [X86][AVX] Add v4i64 shift-by-32 tests

AVX1 could perform this as a v8f32 shuffle instead of splitting - based off PR46621


  Commit: 7bff9bdd34d53a660f80eb1cdc9da885fd2702e1
      https://github.com/llvm/llvm-project/commit/7bff9bdd34d53a660f80eb1cdc9da885fd2702e1
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2021-05-12 (Wed, 12 May 2021)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp

  Log Message:
  -----------
  [X86][AVX] combineConcatVectorOps - add ConcatSubOperand helper. NFCI.

Pull out repeated code to create a concat_vectors of the same operand from all subvecs.


Compare: https://github.com/llvm/llvm-project/compare/c5ec00e62b0e...7bff9bdd34d5