[all-commits] [llvm/llvm-project] c5ec00: [TargetLowering] Improve legalization of scalable ...

[Fraser Cormack via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c5ec00e62b0e7b91eb07e25441c7ed38227f5bf3
      https://github.com/llvm/llvm-project/commit/c5ec00e62b0e7b91eb07e25441c7ed38227f5bf3
  Author: Fraser Cormack <fraser at codeplay.com>
  Date:   2021-05-12 (Wed, 12 May 2021)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    M llvm/lib/CodeGen/TargetLoweringBase.cpp
    A llvm/test/CodeGen/AArch64/sve-widen-scalable-vectortype.ll
    A llvm/test/CodeGen/RISCV/rvv/legalize-scalable-vectortype.ll

  Log Message:
  -----------
  [TargetLowering] Improve legalization of scalable vector types

This patch extends the vector type-conversion and legalization capabilities of
scalable vector types.

Firstly, `vscale x 1` types now behave more like the corresponding `vscale x
2+` types. This enables the integer promotion legalization of extended scalable
types, such as the promotion of `<vscale x 1 x i5>` to `<vscale x 1 x i8>`.

These `vscale x 1` types are also now better handled by
`getVectorTypeBreakdown`, where what looks like older handling for 1-element
fixed-length vector types was spuriously updated to include scalable types.

Widening of scalable types is now better supported, by using `INSERT_SUBVECTOR`
to insert the smaller scalable vector "value" type into the wider scalable
vector "part" type. This allows AArch64 to pass and return `vscale x 1` types
by value by widening.

There are still cases where we are unable to legalize `vscale x 1` types, such
as where expansion would require splitting the vector in two.

Reviewed By: sdesmalen

Differential Revision: https://reviews.llvm.org/D102073