[all-commits] [llvm/llvm-project] 6e876f: [SelectionDAG][Mips][PowerPC][RISCV][WebAssembly] ...

[Jessica Clarke via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6e876f9dedf00b24a96b8781e3b39d5282c43e91
      https://github.com/llvm/llvm-project/commit/6e876f9dedf00b24a96b8781e3b39d5282c43e91
  Author: Jessica Clarke <jrtc27 at jrtc27.com>
  Date:   2021-05-05 (Wed, 05 May 2021)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    M llvm/lib/Target/WebAssembly/WebAssemblyInstrAtomics.td
    M llvm/test/CodeGen/Mips/atomic.ll
    M llvm/test/CodeGen/PowerPC/atomics-i16-ldst.ll
    M llvm/test/CodeGen/PowerPC/atomics-i32-ldst.ll
    M llvm/test/CodeGen/PowerPC/atomics-i64-ldst.ll
    M llvm/test/CodeGen/PowerPC/atomics-i8-ldst.ll
    M llvm/test/CodeGen/RISCV/atomic-signext.ll

  Log Message:
  -----------
  [SelectionDAG][Mips][PowerPC][RISCV][WebAssembly] Teach computeKnownBits/ComputeNumSignBits about atomics

Unlike normal loads these don't have an extension field, but we know
from TargetLowering whether these are sign-extending or zero-extending,
and so can optimise away unnecessary extensions.

This was noticed on RISC-V, where sign extensions in the calling
convention would result in unnecessary explicit extension instructions,
but this also fixes some Mips inefficiencies. PowerPC sees churn in the
tests as all the zero extensions are only for promoting 32-bit to
64-bit, but these zero extensions are still not optimised away as they
should be, likely due to i32 being a legal type.

This also simplifies the WebAssembly code somewhat, which currently
works around the lack of target-independent combines with some ugly
patterns that break once they're optimised away.

Reviewed By: RKSimon, atanasyan

Differential Revision: https://reviews.llvm.org/D101342