[all-commits] [llvm/llvm-project] 6f1761: [RISCV][VP] Lower VP ISD nodes to RVV instructions

[Fraser Cormack via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6f17613bfb95583f96a35ed589b67f07c5b028ab
      https://github.com/llvm/llvm-project/commit/6f17613bfb95583f96a35ed589b67f07c5b028ab
  Author: Fraser Cormack <fraser at codeplay.com>
  Date:   2021-05-05 (Wed, 05 May 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
    M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
    A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
    A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll
    A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll
    A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll
    A llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
    A llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll
    A llvm/test/CodeGen/RISCV/rvv/vsra-vp.ll
    A llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll

  Log Message:
  -----------
  [RISCV][VP] Lower VP ISD nodes to RVV instructions

This patch supports all of the current set of VP integer binary
intrinsics by lowering them to to RVV instructions. It does so by using
the existing RISCVISD *_VL custom nodes as an intermediate layer. Both
scalable and fixed-length vectors are supported by using this method.

One notable change to the existing vector codegen strategy is that
scalable all-ones and all-zeros mask SPLAT_VECTORs are now lowered to
RISCVISD VMSET_VL and VMCLR_VL nodes to match their fixed-length
BUILD_VECTOR counterparts. This allows them to reuse the existing
"all-ones" VL patterns.

To reduce the size of the phabricator diff, some tests are intentionally
left out and will be added later if the patch is accepted.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D101826