[all-commits] [llvm/llvm-project] 8f5cd4: [RISCV] Teach DAG combine what bits Zbp instructio...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8f5cd4940515899b06d6d1ecf593fbd6e08cce20
      https://github.com/llvm/llvm-project/commit/8f5cd4940515899b06d6d1ecf593fbd6e08cce20
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-04-25 (Sun, 25 Apr 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rv32zbp-intrinsic.ll
    M llvm/test/CodeGen/RISCV/rv64zbe-intrinsic.ll
    M llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll

  Log Message:
  -----------
  [RISCV] Teach DAG combine what bits Zbp instructions demanded from their inputs.

This teaches DAG combine that shift amount operands for grev, gorc
shfl, unshfl only read a few bits.

This also teaches DAG combine that grevw, gorcw, shflw, unshflw,
bcompressw, bdecompressw only consume the lower 32 bits of their
inputs.

In the future we can teach SimplifyDemandedBits to also propagate
demanded bits of the output to the inputs in some cases.