[all-commits] [llvm/llvm-project] 7b312e: [NFC][X86][AVX2] Add baseline CodeGen/CostModel te...

[Roman Lebedev via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7b312e228c36fc10cec4ecbd98a289f213a97518
      https://github.com/llvm/llvm-project/commit/7b312e228c36fc10cec4ecbd98a289f213a97518
  Author: Roman Lebedev <lebedev.ri at gmail.com>
  Date:   2021-04-26 (Mon, 26 Apr 2021)

  Changed paths:
    A llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-2.ll
    A llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-3.ll
    A llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-4.ll
    A llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-2.ll
    A llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-3.ll
    A llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-4.ll
    A llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-2.ll
    A llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-3.ll
    A llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-4.ll
    A llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-2.ll
    A llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-3.ll
    A llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-4.ll

  Log Message:
  -----------
  [NFC][X86][AVX2] Add baseline CodeGen/CostModel tests for interleaved loads/stores of i16 w/ strides 2/3/4

`X86TTIImpl::getInterleavedMemoryOpCostAVX2()` currently contains data
only for a handful of tuples. For now, at least add tests for a few more.

I'm guessing that we care how well the patterns codegen since
we use their presumed cost for vectorization decisions,
so i've added codegen tests too.

There's one really easy caveat for these codegen tests:
for interleaved load tests, we really have to ensure that the
deinterleaved vectors are escaped separately. Similarly for stores.