[all-commits] [llvm/llvm-project] fc86e6: [ARM][disassembler] Fix incorrect number of MCOper...

[Min-Yih Hsu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: fc86e6d188c38e2cee221fae4960c3307367f387
      https://github.com/llvm/llvm-project/commit/fc86e6d188c38e2cee221fae4960c3307367f387
  Author: Min-Yih Hsu <minyihh at uci.edu>
  Date:   2021-04-25 (Sun, 25 Apr 2021)

  Changed paths:
    M llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
    A llvm/test/MC/Disassembler/ARM/bl-arm.txt
    A llvm/test/MC/Disassembler/ARM/sub-sp-imm-thumb2.txt

  Log Message:
  -----------
  [ARM][disassembler] Fix incorrect number of MCOperands generated by the disassembler

Try to fix bug 49974.

This patch fixes two issues:

 1. BL does not use predicate (BL_pred is the predicate version of BL),
    so we shouldn't add predicate operands in DecodeBranchImmInstruction.
 2. Inside DecodeT2AddSubSPImm, we shouldn't add predicate operands into
    the MCInst because ARMDisassembler::AddThumbPredicate will do that for us.
    However, we should handle CC-out operand for t2SUBspImm and t2AddspImm.

Differential Revision: https://reviews.llvm.org/D100585