[all-commits] [llvm/llvm-project] 3b8ec8: [X86] Support AMX fast register allocation

[xiangzh1 via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3b8ec86fd576b9808dc63da620d9a4f7bbe04372
      https://github.com/llvm/llvm-project/commit/3b8ec86fd576b9808dc63da620d9a4f7bbe04372
  Author: Xiang1 Zhang <xiang1.zhang at intel.com>
  Date:   2021-04-25 (Sun, 25 Apr 2021)

  Changed paths:
    M llvm/include/llvm/CodeGen/Passes.h
    M llvm/include/llvm/CodeGen/TargetPassConfig.h
    M llvm/lib/CodeGen/TargetPassConfig.cpp
    M llvm/lib/Target/X86/CMakeLists.txt
    M llvm/lib/Target/X86/X86.h
    A llvm/lib/Target/X86/X86FastTileConfig.cpp
    M llvm/lib/Target/X86/X86LowerAMXIntrinsics.cpp
    M llvm/lib/Target/X86/X86LowerAMXType.cpp
    A llvm/lib/Target/X86/X86PreAMXConfig.cpp
    M llvm/lib/Target/X86/X86TargetMachine.cpp
    A llvm/test/CodeGen/X86/AMX/amx-configO0toO0.ll
    A llvm/test/CodeGen/X86/AMX/amx-configO2toO0-lower.ll
    A llvm/test/CodeGen/X86/AMX/amx-configO2toO0-precfg.ll
    A llvm/test/CodeGen/X86/AMX/amx-configO2toO0.ll
    A llvm/test/CodeGen/X86/AMX/amx-fast-tile-config.mir
    M llvm/test/CodeGen/X86/AMX/amx-low-intrinsics-no-amx-bitcast.ll
    M llvm/test/CodeGen/X86/AMX/amx-low-intrinsics.ll
    M llvm/test/CodeGen/X86/O0-pipeline.ll
    M llvm/tools/opt/opt.cpp
    M llvm/utils/gn/secondary/llvm/lib/Target/X86/BUILD.gn

  Log Message:
  -----------
  [X86] Support AMX fast register allocation

Differential Revision: https://reviews.llvm.org/D100026