[all-commits] [llvm/llvm-project] 14cc1c: [RISCV] Implement the vneg.v builtin.

[Kai Wang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 14cc1cb22230de433bb9eb35624355a6d0bef2d2
      https://github.com/llvm/llvm-project/commit/14cc1cb22230de433bb9eb35624355a6d0bef2d2
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2021-04-23 (Fri, 23 Apr 2021)

  Changed paths:
    M clang/include/clang/Basic/riscv_vector.td
    A clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vneg.c
    A clang/test/CodeGen/RISCV/rvv-intrinsics/vneg.c
    M clang/utils/TableGen/RISCVVEmitter.cpp

  Log Message:
  -----------
  [RISCV] Implement the vneg.v builtin.

Differential Revision: https://reviews.llvm.org/D100819