[all-commits] [llvm/llvm-project] 5185b5: [RISCV] Fix crash with fptosi.sat/fptoui.sat intri...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5185b52988c5874dd46b2cc17685b78cd64609c1
      https://github.com/llvm/llvm-project/commit/5185b52988c5874dd46b2cc17685b78cd64609c1
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-04-22 (Thu, 22 Apr 2021)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
    M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
    M llvm/test/CodeGen/RISCV/double-convert.ll
    M llvm/test/CodeGen/RISCV/float-convert.ll
    M llvm/test/CodeGen/RISCV/half-convert.ll

  Log Message:
  -----------
  [RISCV] Fix crash with fptosi.sat/fptoui.sat intrinsics on RV64. Add test cases.

Add PromoteIntOp_FP_TO_XINT_SAT to type legalize the bit width
operand from i32 to i64 for RV64.

Add test cases for the saturating intrinsics for half/float/double
and i32/i64. CodeGen is definitely not optimal. We can probably
make use of the native behavior of fcvt instructions in many cases.

Fixes PR50083