[all-commits] [llvm/llvm-project] 9524a0: [RISCV] Support vector type for second operand of ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9524a0553d82cbbddf5541cbfb19937cfb107daa
      https://github.com/llvm/llvm-project/commit/9524a0553d82cbbddf5541cbfb19937cfb107daa
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-04-22 (Thu, 22 Apr 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/test/CodeGen/RISCV/rvv/vmfge-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmfge-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmfgt-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmfgt-rv64.ll

  Log Message:
  -----------
  [RISCV] Support vector type for second operand of vmfge and vmfgt IR intrinsics.

We don't have instructions for these, but can swap the operands
to use vmle/vmflt. This makes the IR interface more consistent and
simplifies the frontend implementation.

Part of D100925


  Commit: d77d56acfd48e8253a35d885db8daac78793313f
      https://github.com/llvm/llvm-project/commit/d77d56acfd48e8253a35d885db8daac78793313f
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-04-22 (Thu, 22 Apr 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsgt-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll

  Log Message:
  -----------
  [RISCV] Add missing tests for vector type for second operand of vmsgt and vmsgtu IR intrinsics.

Refactor to use new multiclass instead of individual patterns.

We already supported this due to SEW=64 on RV32, but we didn't have
test cases for all the types we supported.

Part of D100925


  Commit: e01c419ecdf5511c550c3ec9d9c9dd132b480e88
      https://github.com/llvm/llvm-project/commit/e01c419ecdf5511c550c3ec9d9c9dd132b480e88
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-04-22 (Thu, 22 Apr 2021)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    A llvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vmsge-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv64.ll

  Log Message:
  -----------
  [RISCV] Add IR intrinsics for vmsge(u).vv/vx/vi.

These instructions don't really exist, but we have ways we can
emulate them.

.vv will swap operands and use vmsle().vv. .vi will adjust the
immediate and use .vmsgt(u).vi when possible. For .vx we need to
use some of the multiple instruction sequences from the V extension
spec.

For unmasked vmsge(u).vx we use:
  vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd

For cases where mask and maskedoff are the same value then we have
vmsge{u}.vx v0, va, x, v0.t which is the vd==v0 case that
requires a temporary so we use:
  vmslt{u}.vx vt, va, x; vmandnot.mm vd, vd, vt

For other masked cases we use this sequence:
  vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0
We trust that register allocation will prevent vd in vmslt{u}.vx
from being v0 since v0 is still needed by the vmxor.

Differential Revision: https://reviews.llvm.org/D100925


Compare: https://github.com/llvm/llvm-project/compare/37e145812855...e01c419ecdf5